As shown in FIG. 1 and FIG. 2, a low temperature poly-silicon (LTPS) transistor array substrate in the prior art comprises a substrate 1, a poly-silicon semiconductor active region 2 provided on the substrate 1, and a gate 4 insulated from the poly-silicon semiconductor active region 2, wherein a gate insulating layer 3 is provided between the gate 4 and the poly-silicon semiconductor active region 2, and the gate insulating layer 3 is etched twice during respectively forming patterns of the gate insulating layer 3 and the gate 4 through patterning processes. As a result, the gate insulating layer 3 has reduced density, and has an interface defect at the interface in contact with the poly-silicon semiconductor active region 2.
As shown in FIG. 1, an LTPS transistor array substrate comprising an N-type metal-oxide-semiconductor (NMOS) transistor further comprises a source-drain extension region 5 and a source-drain doping region 6 which are successively provided at each of both sides of the poly-silicon semiconductor active region 2, wherein firstly, the source-drain extension regions 5 (comprising formed low energy shallow junctions) are formed by implanting medium or low dose of ions such as phosphorus or arsenic ions by using a mask of the gate 4, and then the source-drain doping regions 6 are formed by implanting large dose of dopant ions with a mask.
The source-drain extension region 5 forms a gradually varied lateral ion concentration gradient between the source-drain doping region 6 of high ion concentration and a channel region of the poly-silicon semiconductor active region 2 of low ion concentration. The lateral ion concentration gradient of the source-drain extension region 5 decreases the electric field between the junction and the channel region, and separates a position with maximum electric field in the junction from a path with maximum current in the channel, in order not to generate hot carriers.
However, even if the source-drain extension region 5 is provided, the leakage current in the source-drain extension region 5 and the poly-silicon semiconductor active region 2 is still large, especially in a portion of the source-drain extension region 5 in contact with the poly-silicon semiconductor active region 2.
As shown in FIG. 2, the LTPS transistor array substrate comprising a P-type metal-oxide-semiconductor (PMOS) transistor further comprises a source-drain doping region 6 provided on each of both sides of the poly-silicon semiconductor active region 2, wherein the source-drain doping regions 6 are formed by large dose implantation. In this case, there is no gradually varied lateral concentration gradient between the source-drain doping region 6 and the poly-silicon semiconductor active region 2. Therefore, the concentration gradient is large, and hot carriers are easily generated.